The volume of data handled by network devices has increased dramatically over the past decade, resulting in significant challenges in terms of designing bigger and faster switches/routers to keep up with increasing bandwidth demands. The total off-chip bandwidth of the switching/routing chip C is the product of the total number of ports per chip R (referred to as the radix of the chip) and the per port speed B (C=R×B). Increasing the total off-chip bandwidth C requires increasing the radix of the chip R and/or the per port speed B. However, there is a trade-off between these two parameters in terms of electronic integrated circuit (IC) design.
It is difficult to increase the total off-chip bandwidth C of an IC switching/routing chip. First, the length of on-chip interconnects generally governs the speed between ports. The smaller the size of the chip, the faster the speed the interconnects can support. Therefore, a smaller chip may be able to support higher port speeds, but only at the cost of lower port count due to the smaller chip area (and hence limited pin count; of which power supplies typically consume almost half of the pins). Second, the input/output (I/O) port power density typically does not scale with the transistor technology. Even if the transistor technology supports higher speed and lower power, the I/O power increases as the port speed increases. More effective on-chip equalization components are needed to drive signals across a reasonable length of the electrical transmission channels at higher speeds, each of which produces additional heat. Since there is a maximum heat dissipation capacity for a given die size, the port count is reduced to fit into the power envelope for increased per port speed. To avoid these issues and achieve higher switching capacity per node, one common practice is to connect multiple chips in a non-blocking fashion inside a chassis to form a node with a relatively larger aggregate switching capacity. However, this approach has its own limitations, as the distance over the chassis backplane's Printed Circuit Board (PCB) that a switch chip I/O can drive signals becomes shorter as the I/O rate increases. Another general practice is to interconnect multiple small chassis together in a non-blocking fashion to form a virtual chassis with larger switching capacity. This approach is the least integrated, hence the most expensive and power hungry because it represents a significant overhead in terms of packaging materials and interconnects between chassis, and also poses many challenges in terms of deployment and operations.
Arrayed waveguide gratings (AWGs) have been used as interconnection fabrics in all-optical routers and optical-electrical hybrid routers. A known implementation includes single AWG devices or two cascaded AWGs with optical label switching, all optical wavelength converter(s) and shared optical delay line buffers. This system is limited by the size of the AWG and is difficult to scale. In addition optical delay line buffers, which are typically very small, are generally insufficient to make the router of practical use. The two-stage cascaded design makes use of one AWG to solve packet contention rather than scaling up the port count. Other known implementations include four layers of 4×4 AWGs and shared CMOS RAM to provide a single stage design with multiple layers of AWGs; however, this design does not result in a non-blocking fabric, making the design inefficient and unappealing from a practical deployment perspective. This approach is also very difficult to scale due to the complexity and limitations of the shared RAM architecture.